When an instruction or operation is executed in a portable information terminal device, a CPU (central processing unit) can access an external memory. The system performance of CPUs has been improved so that there has been a desire for a CPU to acquire instruction data from an external memory faster, however, improvement of the performance of peripheral devices has not caught up with CPUs at present.
In order to address this problem, a cache memory can be installed to increase the system performance. A cache memory can be a fast memory such as a static random access memory (SRAM) that stores data between a CPU and main memory. In order to improve system performance, instruction data, which is frequently used, is stored in the cache memory.
If instruction data requested by a CPU is in cache memory, fast access is possible. A cache memory includes, for example, a memory area arranged with memory cells arranged in lines of data. A line of data can be accessed in accordance with an address match between an externally applied address and a TAG (address stored on the cache corresponding to the location of the line of data in main memory).
In a cache memory, instruction data which is located near an address that has been accessed once is likely to be subsequently accessed due to the time and spatial local property of a program. As the number of bits of data in a line of cache is increased, so that plural data request can be satisfied with access of a single line of data, system performance may be improved.
If data requested is not in the cache memory (cache miss), an external memory should be accessed. Such a cache miss, comes with a heavy speed penalty. When there is a cache miss, a refill data operation is performed in which a line of data in a cache is refilled with data from the main memory, including the data requested. If one line has a large amount of data at this time, the refill data provided from an external memory in response to a request from the CPU is increased, thus, system performance decreases. On the other hand, if one line of data is decreased, this refill time penalty decreases. However, as the data in a line decreases, the number of tags (used to verify data requested is in the cache) increases, thus increasing the area of the cache.
A conventional control apparatus for a cache memory having such characteristics will now be described with reference to FIG. 5. Referring to FIG. 5, a conventional cache memory control apparatus and cache memory is set forth in a circuit schematic diagram.
Conventional cache memory control apparatus 10 controls a cache memory 100 as one of various control functions of a CPU. Conventional cache memory apparatus 10 includes a control section 11, a comparator 107, a selector 114, an inverter 119, and an OR gate 400.
Cache memory 100 holds, for example, instruction data which is frequently used on the main memory by the CPU. Cache memory 100 includes a DATA portion 101, a TAG portion 102, and a valid bit 103. DATA portion 101 holds instruction data. TAG portion holds an address (main memory address) at which the instruction data is located. Valid bit 103 represents the validity (valid/invalid) of a line.
For example, when an address 104 for requesting reading of a line 118 of cache memory 100 is provided from control section 11, comparator 107 compares an address 105 read from TAG portion 102 for line 118 which is designated by lower bits of address 104 with upper bits 106 of the address 104. At the same time, valid bit 103 for line 118 is read. A hit/miss result signal 300 of a hit (hit/miss) is output to the control section 11. Hit/miss result signal 300 indicates a hit to control section 11 when valid bit 103 is valid and the comparison result is a match. Hit/miss result signal 300 indicates a miss to control section 11 when the valid bit 103 is invalid or the comparison result is not a match.
Hit/miss result signal 300 becomes active to indicate a miss. The miss is called a cache miss. At the time of a cache miss, an operation for reading data at the same address as the requesting address is executed on an external memory. The data read from the external memory is written into the cache memory in a refill process.
When the cache access is a hit, a read operation of DATA portion 101 is immediately executed. However, when the cache access is a miss, the read operation of DATA portion 101 is not performed until after the refill process is completed. Writing of the DATA portion 101 is executed in accordance with a write enable 121 of DATA portion 101 which is output from control section 11.
A write enable 108 for enabling/disabling writing of write data 113 to TAG portion 102 and valid bit 103 becomes active when control section 11 provides a refill end signal 111 or an invalid instruction signal 112 to OR gate 400. The refill end signal 111 indicates the end of a refill process and becomes active when the refill process is finished. Invalid instruction signal 112 indicates an instruction to make cache memory 100 invalid and becomes active when an instruction to make cache memory 100 invalid is made.
Data to be written in TAG portion 102 and valid bit 103 is write data 113. Either valid data 116 or invalid data 117 selected by a selector 114 becomes write data 113. Valid data 116 is data indicating an address to be written in the TAG portion 102 to be updated and the validity of a line to be written in valid bit 103. Invalid data 117 is data of “0” to be written in TAG portion 102 and valid bit 103.
Selector 114 is supplied with refill end signal 111 directly and through inverter 119 as a select signal. Selector 114 selects valid data 116 when refill end signal 111 is active (high level) and selects invalid data 117 when refill end signal 111 is inactive (low level).
Control section 11 generates a refill data request signal 110. Refill data request signal 110 requests refill data from an external memory (not illustrated) at the time of a cache miss. When refill data request signal 110 becomes active, refill data is requested.
Next, the operation of a conventional refill process at the time of a cache miss will be describe with reference to FIG. 6. Referring now to FIG. 6, a block diagram showing the connection structure of a cache memory 100 incorporated in a CPU 130 and an external memory 200. Constituents in FIG. 6 having corresponding constituents in FIG. 5 are referred to by the same reference character. It is assumed that cache memory control apparatus 10 of FIG. 5 is incorporated in CPU 130.
In FIG. 6, in a case where CPU 130 accesses an external device such as a memory (external memory 200, in this example), a BIU (bus interface unit) 201 interfaces with address data 202. When a miss occurs in line 118 (for example) of cache memory 100, refill data request signal 110 becomes active. The active refill data request signal 110 is sent to BIU 201 via a bus 203 and on to external memory 200 via a system bus 204.
In external memory 200, refill data 205 at an address (202) is read to provide refill data 205 to BIU 201 via a system bus 206. Refill data 205 may then be provided to cache memory 100 from BIU 201 via a bus 207 and written into DATA portion 101. At this time, TAG portion 102 and valid bit 103 for line 118 (where the miss occurred) are updated at the same time as the last of the refill data is written.
Referring to FIG. 7, a timing diagram illustrating timings of individual data at the time of a conventional refill operation is set forth.
The timing diagram of FIG. 7 illustrates a clock 1 shown as (a), a cache miss 300 shown as (b), a refill data request 110 to external memory shown as (c), an address 202 on cache shown as (d), an address 202 received by BIU shown as (e), a clock 2 shown as (f), a system bus 204 (BIU to memory) shown as (g), a system bus 206 (external memory to BIU) shown as (h), data 205 received by BIU shown as (i), data 205 on BIU—cache bus shown as a write enable 121 to cache data portion shown as (k), write data 113 to cache TAG portion 102 and valid bit 103 shown as (1), and write enable 108 to cache TAG portion 102 and valid bit 103 shown as (m).
Referring to FIG. 7 in conjunction with FIGS. 5 and 6, it is assumed that CPU 130 is operating with clock 1 shown as (a) in FIG. 7. Assuming that comparator 107 which generates hit/miss result signal 300 judges that access of line 118 of cache memory 100 is a miss (TAG data 102 does not match address received), hit/miss result signal 300 shown as (b) becomes active (high) indicating that a cache miss has been detected. CPU 130 receives the active hit/miss result signal 300.
Then, in a period S1, CPU 130 sends refill data request signal (pulse signal) 110 to BIU 201 to request refill data from external memory 200 at a miss-occurred address (202) shown as (c). Also in period S1, cache memory 100 outputs the miss-occurred address (202) to bus 203, illustrated as (d) in FIG. 7, to BIU 201. In BIU 201, address (202) is received in synchronism with clock 1 (shown as (e) in FIG. 7) of a period S2.
Further, in a period S3, a clock 2 (shown as (f) in FIG. 7), which is a frequency-divided version of clock 1, is output to system bus 204 that connects BIU 201 to external memory 200 (shown as (g) in FIG. 7).
Then, when refill data 205 from address (202) in external memory 200 is returned to BIU 201 via system bus 206 (shown as (h) to (j) in periods S4 to S7), CPU 130 outputs write enable 121 to DATA portion 101 (shown as (k) in FIG. 7). In this way, refill data 205 is written to DATA portion 101 in the returned order in periods S8 to S11.
In period S11, the last refill data 3 is written and write enable 108 is output (shown as (m) in FIG. 7), after which TAG portion 102 and valid bit 103 are updated with write data 113 (shown as (l) in FIG. 7).
In the conventional cache memory control apparatus, however, there may be a case where, for example, a portable information terminal device to which cache memory control apparatus 10 is adapted will not recover for some factors unless the CPU is reset. Resetting may be made at various timings.
There is a case where resetting can be done in a state to be described below at the time of performing a refill process for a cache miss. Because in the above-described conventional approach 16 bytes of data returned in several clocks from external memory 200, there is a case where resetting may be done in a state where some of the data previously returned in periods S4 to S6 has been written in DATA portion 101 and the remaining data and TAG portion 102 have not been updated.
At this time, if a TAG of the previous line is valid, the refill data already written becomes data with respect to the previous valid TAG and the contents of that line are not valid or in error. After reset recovery, therefor, it is not known which line has the erroneous data.
Because of the reason above, when resetting is done, all lines of cache memory 100 are made invalid in the conventional approach. In this case, to make the 1st through 1024th line invalid, for example, a loop of making the 1st line invalid, incrementing the address and determining if the address is the 1024th line is carried out until al lines are made invalid. This approach would take several hundred clock cycles. Valid data that have been in lines other than the miss-loaded (incompletely loaded) line before resetting is done are all made invalid.
Therefore, there may be a case where cache memory 100 cannot be recovered to the state before the resetting operation, and even if recovery were possible, it would take considerable time.
In view of the above discussion, it would be desirable to provide a cache memory control apparatus and a processor, which may recover a cache memory to a state before resetting as quickly as possible even if resetting is done when refilling data in response to a cache miss.